Patil - VLSI Designer - Kariyammana Agrahara, Bellandur, Bangalore, Karnataka 560103, India

Netravati Patil

Kariyammana Agrahara, Bellandur, Bangalore, Karnataka 560103, India

Services

VLSI Designer

  • Full time
  • Part time
  • One time
  • Contract
  • Temp

Summary:

RTL designing ,unit level verification, Spyglass checks, Formality checks, synthesis, STA, Redhawk Power analysis and also Co-Simulation in cadence environment
Tools : Synopsys-VCS, ncsim, Dc_shell, cadence, spyglass.

Work History

Digital Design Engineer

LSI India Research & Development Pvt. Ltd

From July 2013

Qualifications & Certifications

National Institute of Technology

Electronics and Communication Engineering

Poojya Doddapaa College of Engineering

Pre-University

Shree Guru PU Independent College

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