VLSI Design & Verification
- Full time
- Part time
- One time
Experience Presently: SITAR-VLSI (Growell Hr. Solutions)
HDLs : Verilog and VHDL
HVL :System Verilog.
Verification Methodology :Coverage Driven Verification, Assertion based Verification.
EDA Tool :Modelsim and ISE
Domain:ASIC/FPGA Design Flow, Digital Design methodologies
Knowledge :RTL Coding, Simulation,Code Coverage, Functional Coverage, Synthesis.
Society for Integration Circuit and Applied Research(SITAR)
From January 2012
Qualifications & Certifications
Appa Institute of Engineering & Technology
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