Asic Design Engineer
- Full time
- Part time
- One time
Currently working on ARM buses like AHB. Good knowledge on AXI, APB. Proficient in Full custom, semi custom and FPGA flow, working experience on tools such as Modelsim, calibre, IC compiler, Xilinx, Primetime.
From July 2011
Frontend/Backend training done in RV-Vlsi for 8 months
Student at RV-VLSI Design center
RV-VLSI Design Center
July 2011 - July 2011
RTL coding in verilog on either linux platform or windows,
synthesis and STA, DFT
Designing Arbiter which can support 32 masters and 32 slaves, and supports slaves which has split and retry response.
Priority Handling and Grant generation is Completed, working on address decoding for instantiating master and slaves.
Qualifications & Certifications
Jawaharlal Nehru Technological University
SIR. C.R.R Polytechnic College
PG in VLSI design
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