Gagrani - Electronics & Communication Engineer - Chennai, TN, India

Mohit Gagrani

Chennai, TN, India

Services

Electronics & Communication Engineer

  • Full time
  • Part time
  • One time
  • Contract
  • Temp

Summary:

Xilinx

Work History

VIT University

Robosapiens India

Projects

an IEEE paper on "A multi parametric optimization based novel approach for an efficient Design Space

High level synthesis (HLS) is the methodology of generating RTL design taking into consideration the behavioural specification and constraints within an optimized cost function. Design space exploration (DSE), an important stage of HLS, is a task for identifying and evaluating design alternatives during system development for obtaining Pareto optimal solution. Concerns over the power dissipation coupled with the conventional metrics such as area, time delay, thermal, performance, reliability, cost and testability have raised the demand for an efficient technique of high level synthesis with better design space exploration. This paper presents a novel approach to achieve a Pareto optimal solution for this design space exploration in minimum possible design time using Greedy Algorithm and Priority Factor (PF) for power and timing analysis.

Design and implementation of a single balanced diode balanced mixer.

In this Project, we designed a single balanced diode balanced hybrid mixer and did an analysis of a LO/RF and LO/IF isolation and conversion loss.

Software implementation of an ATM machine.

In this Project, we did a software Implementation of an ATM machine using software Keil.

Speech Compression Using Linear Predictive Coding (LPC) and Differential Pulse Code Modulation (DPCM

In this project, our objective was to compress our speech signal using two different methods namely-Predictive Coding and DPCM. For predictive coding we used Linear Predictive Coding Method using Levinson-Durbin Recursion algorithm.

Implementation of Booth Multiplier Algorithm in Verilog.

In this project an 8x8 multiplier was designed and simulated at the gate level and at the transistor level using Xilinx.

Design of SHA-1 Hashing Algorithm based on FPGA using Xilinx

In this project, a hardware based SHA1 Hashing Algorithm is designed and implemented using the hardware description language Verilog.

A multi parametric optimization based novel approach for an efficient Design Space Exploration for A

High level synthesis (HLS) is the methodology of generating RTL design taking into consideration the behavioural specification and constraints within an optimized cost function. Design space exploration (DSE), an important stage of HLS, is a task for identifying and evaluating design alternatives during system development for obtaining Pareto optimal solution. Concerns over the power dissipation coupled with the conventional metrics such as area, time delay, thermal, performance, reliability, cost and testability have raised the demand for an efficient technique of high level synthesis with better design space exploration. This paper presents a novel approach to achieve a Pareto optimal solution for this design space exploration in minimum possible design time using Greedy Algorithm and Priority Factor (PF) for power and timing analysis.

Design and implementation of a single balanced diode balanced mixer.

In this Project, we designed a single balanced diode balanced hybrid mixer and did an analysis of a LO/RF and LO/IF isolation and conversion loss.

Software implementation of an ATM machine.

In this Project, we did a software Implementation of an ATM machine using software Keil.

Speech Compression Using Linear Predictive Coding (LPC) and Differential Pulse Code Modulation (DPCM

In this project, our objective was to compress our speech signal using two different methods namely-Predictive Coding and DPCM. For predictive coding we used Linear Predictive Coding Method using Levinson-Durbin Recursion algorithm.

Implementation of Booth Multiplier Algorithm in Verilog.

In this project an 8x8 multiplier was designed and simulated at the gate level and at the transistor level using Xilinx.

Design of SHA-1 Hashing Algorithm based on FPGA using Xilinx

In this project, a hardware based SHA1 Hashing Algorithm is designed and implemented using the hardware description language Verilog.

Qualifications & Certifications

VIT University

mhs,tilak nagar,jaipur

Vit University Chennai

bansal classes, jaipur

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