- Full time
- Part time
- One time
VLSI PHYSICAL DESIGN,DIGITAL DESIGN LOGIC.
Timing Driven Layout Using 64 Macros ON 28nm TECHNOLOGY.
• Objective: Timing Driven Layout Using 64 Macros ON 28nm TECHNOLOGY.
Tools : SOC Encounter & ETS.
Gate count : 120285
Blocks : 64
No. of Clocks : 01
Frequency : 650 MHz
Responsibility: Responsible for taking the design through floor planning, placement, Clock Tree Synthesis and Routing.
Macro placement was critical, placement congestion issues.
Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trail Route, Power analysis, Timing analysis, Adding Filler Cells, Timing analysis.
Qualifications & Certifications
BACHELOR OF TECNOLOGY
Electronics and Communications Engineering
Board of Intermediate Education Sri Chaitanya Junior College
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