Gogula - VLSI Designer - Bangalore, KA, India

Manikanta Gogula

Bangalore, KA, India

Services

VLSI Designer

  • Full time
  • Part time
  • One time
  • Contract
  • Temp

Summary:

VLSI PHYSICAL DESIGN,DIGITAL DESIGN LOGIC.

Projects

Timing Driven Layout Using 64 Macros ON 28nm TECHNOLOGY.

PROJECT PROFILE


PNR Project:

• Objective: Timing Driven Layout Using 64 Macros ON 28nm TECHNOLOGY.

Tools : SOC Encounter & ETS.
Gate count : 120285
Blocks : 64
No. of Clocks : 01
Frequency : 650 MHz
Responsibility: Responsible for taking the design through floor planning, placement, Clock Tree Synthesis and Routing.

Issues Resolved:
Macro placement was critical, placement congestion issues.
Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trail Route, Power analysis, Timing analysis, Adding Filler Cells, Timing analysis.

Qualifications & Certifications

BACHELOR OF TECNOLOGY

JNTU KAKINADA

Electronics and Communications Engineering

J.N.T.U University

Board of Intermediate Education Sri Chaitanya Junior College

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