Mounika - Bachelor Of Technology - New Delhi, DL, India

Madam Mounika

New Delhi, DL, India


Bachelor Of Technology


i am the electronics engineering student


High Speed ASIC Design Of Complex Multiplier Using VEDIC Mathematics

The idea for designing the multiplier and adder, subtractor unit is adopted from ancient Indian mathematics "Vedas." On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay, dynamic power consumption comparison with DA based architecture and parallel adder

Qualifications & Certifications

bachelor of technology

ARJUN college of Technology & Sciences

Sri Chaitanya Junior College

Saidaiah Concept School

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