Product and Test Engineering
From August 2010
Manage a group of test engineers and product lot disposition team AEs.
* Lead test engineering team to set up new test capability and support in house test setup for new test technology ramp up.
* Overall core competency leaders for PTE department.
* PTE coordinator to co-work with NXP to setup fault diagnostic tools (FALOC and TESSENT) for memory bitmap and digital scan test for key volume products
* 2012 successfully apply project management skill leading the cross functional team set up the new SPEA tester capability for the high voltage products within the project timeline for automotive products.
* Lead a team of AEs support product engineers on the daily first level low yield analysis and embark productivity projects.
* Successfully completed 9 projects with FTE gain in 2013 and identified 11 projects potential FTE gain in 2014.
* Setup the core competency matrix and assessment criteria for the different domains (RF, Non Volatile and High voltage).
* Successfully partnership with HR, setup the core competency learning and assessment into e-system.
* Cross train lot disposition to test engineering for resource optimization.
* Cross training and productivity has allow avoidance to hire one AE who resign for full time degree.
) process/ product transfer project. and various business processes (2009)Spearheaded LDT on One Button Yield Manager project; automation for basic low yield analysis within 6 months; strategically allocated resources and resulted in 1.5 head counts savings (2010)
* Company SRC (Sport & Recreation) for 2012-13 Recreation team leaders. Successfully organize 2 local and 1 overseas recreation events and D&D and family days with overwhelm respond
PRINCIPAL PRODUCT ENGINEER
Product and Test Engineering
From August 2003
Manage all facets of yield improvement through yield analysis and failure analysis on CMOS18/C14/C14NV (non-volatile) process devices
* Communicate and liaise with overseas test houses and customers to resolve low yield issues due to test issues
* Act as technical interface between Fab and customers through regular conference calls and customer visits
* Selected to oversee handling of automotive maverick and PPM reduction projects
* Lead and mentor up to six new Senior Engineers and Engineers within NXP group
* Strategise and manage FALOC logic and bitmapping project; involved setup of regular training from NXP CTO group; identifying and implementing products with bitmap and logic mapping capability
* Managed lot disposition team (LDT) in performing first level low yield analysis for Engineers
* Lead Lot disposition team (LDT) achieved savings through automation of Lot disposition routine tasks and streamlining current process flows and eliminated non value-added processes
* Acted as Project Lead for new niche technology Qubic4 (BICMOS) process and transfer projects
* Analyse and propose training needs and capability build up for RF products
* Coach engineers in identifying silicon yield gap and execute improvement activities with Process Development Team for the Qubic4 (BICMOS) process & product transfer project.
* Awarded numerous awards including STAR OJT Mentor Award (2008) and three recognition awards for outstanding contributions to various business processes (2004).
* Successfully led Product Information Display System project; a one-stop intranet access for product information and yield data; accomplished project within 3-month timeline (2007)
* Played pivotal role in revamp of eRMA from QA; E-system for return of material handling; successfully launched system within 4 months and 3hr/weeks time savings (2009)
SENIOR PRODUCT ENGINEER
Chartered Semiconductor Manufacturing
September 1999 - August 2003
(Process Integration/Yield Department)
* In-charge of identifying causes of low sort yield and ETEST failure through systematic analysis
* Liaised with process integration (PI) department to fine tune processes and defect reductions, and oversee new products qualification and yield improvement/stabilisation
* Oversaw application of fault isolation techniques sing tools on Microscopic emission liquid crystal, fluorescent Micro-thermal imaging and C-SAM
* Analysed problems and applied appropriate FA techniques (XSEM, delayer, TEM or FIB) to identify root causes of rejects
* Led team of technicians in carrying out house wafer sort on SRAM test chips using memory test system, MOSAID; liaised with customers and vendors on program release and various versions
* Performed Bitmap on rejects using GDSII layout to locate possible failures on SRAM
* Participated and supported qualification of quarter micron technology; successfully increased up prototype yield from 14% to 75%
* Single-handedly managed and trained technicians to accomplish wafer sort task through consistent coaching and motivation
TEST PRODUCT ENGINEER
Infineon Technologies Asia Pacific
September 1995 - September 1999
* Managed all facets of product transfers and modification of test program on TERADYNE and LTX systems
* Oversaw smooth production, yield improvement and line sustaining; embarked on continuous improvement projects
* Successfully accomplished throughput improvement projects for A360 testers; increased testing speed by 20% using PC emulation software; resulted in company savings of $300,000
* Completed test flow reduction for top volume projects as part of product transfer team from MAL to SIN for high power devices; achieved 60% test cost savings
Qualifications & Certifications
Nanyang Technological University
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