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Saha -  - USA

Joydeep Saha

USA

Work History

Link

From May 2014

Designed 64bit CPU, Area: 500 um x 196 um, Clock Period: 1.5ns, adapted to perform basic instructions like Add, Divide, AND,
OR, XOR, Store Word, Load Word and put to use in Single and Multicycle CPU. Maximum Clock Frequency 3ns to avoid setup and hold
time issues. Adder speed 3.2ns and Divider speed 4ns.(Link)

SRAM Design

January 2014 - March 2014

• The verification of correctness of random and successive writes to and reads from random memory locations with proper sizing.
• Strategies such as a single 16 bit wide Sense Amplifier and single write Circuit implemented instead of 256 bit wideversion to save area of the circuit and minimize power*area* delay Product. Circuit clock period as 1ns optimum with active low read and active
high write enable.
• PERL script for vector file generation and cadence Simulation of SRAM, Functional Verification
Designed the schematic, Checked the functionality and Simulated adders by a TestBenchWaveform

Pipelined Processor

BIT MIPS

From November 2013

A 32- bit MIPS processor having a 5-stage pipeline was implemented in Verilog to support in order execution of MIPS instructions
taking care of RAW and branch hazards.
• Implemented the code in RTL and analysis of the design was performed.

Verilog

From November 2013

• Using a pipelined system, a series of simple instructions are to be executed similar to execution in a CPU.
• Data dependencies are taken care by designing appropriate forwarding unit (FU) and hazard detection unit (HDU).

Title: 2 Input 1 Output Arbiter to achieve fair arbitration for two 4 bit data Transmission (Link) August 2013 - December 2013
• Designed and implemented a 2 input 1 output Arbiter to achieve arbitration for two 4-bit data transmission.
• Designed the finite state machine and the micro-architecture thereafter included the implementation of it in schematic and layout.
• Analyzed Rise Time, Fall Time, Propagation Delays and Verified Circuit so as to meet minimum Setup Time and Hold Time
slack.
• The verification of correctness of timing issues followed by LVS match and DRC check.
• Delay of Data Path Unit 1 clock. Clock period set to a minimum 2ns for preventing setup and hold time violation, Area
minimum=11327.7 µm2

Programmer Analyst/Engineer Trainee

Cognizant Technology SolutionsPrivate Limited

December 2012 - August 2013

(CTS), India www.cognizant.com
• Trained on Basic UNIX, LINUX, UNIX Shell Scripting, SQL and Java, IP4 and IP6, DHCP, etc December2012-August2013
Qualified for project under JPMorgan (client).Certificate of Appreciation for outstanding performance during my tenure.
TECHNICAL SKILLS
• High Level Language: C, C++, Java • Operating Systems: Windows, MAC, Linux
• Scripting Language: Perl, UNIX Shell Scripting • Circuit Simulators: Xilinx(familiar), Circuit Maker, Cadence
Virtuoso
• Hardware Language: Verilog, Python(familiar) • Engineering Software: MATLAB, Zeeland IE3D
GRADUATE LEVEL PROJECTS

UNDERGRADUATE RESEARCHPROJECTS

June 2012 - September 2012

(ONLY IEEE INTERNATIONAL PUBLICATIONS)
• "A Novel Connectivity Control Scheme for Next Generation Wireless System by using Short Coverage Antennas",
IEEE WOCN 2012IIT Indore, India, Sept. 2012 June 2012-Sept 2012
• A Region Based Channel Allocation Scheme for LEO Satellite Communication", IEEE WOCN 2012

IIT

June 2012 - September 2012

Qualifications & Certifications

Engineering and Management

West Bengal University of Technology

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